1. Field of the Invention
The present invention relates to a semiconductor device system configured of semiconductor devices operating in synchronism with a clock or, in particular, to a semiconductor memory system using synchronous memories for retrieving an input signal at a predetermined timing regardless of fluctuations in ambient temperature or in source voltage by adjusting the timing of the clock.
2. Description of the Related Art
In a large-scale semiconductor device system such as a computer using semiconductor devices, various parts thereof are configured to operate in synchronism with a clock, and signals such as data signals and address signals are input and output in synchronism with a clock signal. In recent years, the increased speed of the CPU clock and the processing speed of various other electronic circuits has made it necessary to increase the operating speed of the interfaces connecting the semiconductor devices. An SDRAM is a semiconductor device intended to meet such a demand for higher speed, and can be used at a very high access rate when accessing continuous addresses. The result is that signals on the data bus undergo a change in very short cycles, and it is necessary to retrieve the data bus signals at high speed.
In a memory system, the clock, the commands, the address signals and the write data output from a controller are transmitted along signal lines arranged in parallel with each other. Therefore, the phase relationship between the signals output from the controller is considered to be maintained when the signals are received by a memory. The memories thus could retrieve the other signals at a normal timing in synchronism with the received clock. When reading the data stored in a memory, the data read from inside the memory based on the command and the address signal retrieved are output by the memory in synchronism with the clock. The read data and the clock, however, are transmitted in opposite directions, so that the read data and the clock are considerably displaced from each other when they reach the controller. In addition, the amount of displacement depends on the particular memory from which the data are read.
In the case where a semiconductor device retrieves an input signal, a period when the input signal is required to be established is predetermined before and after the timing of retrieval. The period before the retrieval timing when the input signal is required to be established is called a set-up time, and the period after the retrieval timing when the input signal is required to be established is called a hold time. In the case where the data transfer rate is low with a long data transition period, the above-mentioned displacement, if any, poses no serious problem in view of the fact that a sufficiently long set-up time and hold time can be secured. Suppose, for example, that the signal advances at the rate of about 30 cm per 1 ns. If the signal line between a controller and a memory is 30 cm long, a skew (displacement) of about 2 ns develops. In the case where the clock is 50 MHz and data changes for every clock period, the data transition period is 20 ns, so that a skew of up to about 2 ns can normally be overcome. If the data transition period is further shortened, however, the resulting skew cannot be neglected.
The problem of displacement of the read data in the controller can be solved by arranging a clock source far from a controller and by transmitting the clock along the clock signal line in the same direction as the read data is transmitted to the controller. Nevertheless, a new problem arises that the write data output from the controller is displaced from the clock in each memory. In view of this, this configuration further includes a write clock signal line for transmitting the write clock in the direction away from the controller, wherein the controller generates a write data from a read data and applies it to the write clock signal line. In this way, the read data arriving at the controller from the memory is synchronized with the the read clock, and the write data and other signals arriving at the memory from the controller are synchronized with the write clock. The result is that the controller can retrieve the read data in synchronism with the read clock, and the memory can retrieve the write data in synchronism with the write clock, thus reducing the displacement and making possible a high-speed data transfer.
In this system, the controller can retrieve the read data and the memory can retrieve the write data at a proper timing. However, two clock signal lines for the write and read operations are required, resulting in an increased size of the chip set constituting the controller and an increased number of memory terminals for a larger wiring space.